1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a memory capable of reducing power consumption.
2. Description of the Background Art
Recently, the network increasingly becomes fast, so that a communication terminal such as a rooter or a switch needs to respond to its speed. In general, as for the communication terminal such as the rooter or switch, a memory such as a packet buffer is always put in an activated state (activated) even when a band of communication data considerably differs in height, and the band is low.
In addition, in tandem with the increase in speed of the network, there is an increase in data transfer rate of a network processor and the packet buffer, so that capacity of the memory used as the packet buffer needs to be higher. Thus, in order to respond to the increase in speed of the network, a memory needs to be high in speed and high in capacity.
In order to solve the above problem, the following technique is known.
According to Japanese Patent Laying-Open No. 2003-248652, it is an object to provide a low power consumption and high performance DMA controller that can provide a DMA request with priority and a parameter such as timing information and cancel information, reserve the parameter in advance, and execute DMA transfer according to the set parameter, and that is small in circuit scale, easy to design, and excellent in data transfer efficiency. A main memory used to store various kinds of data is physically divided into a plurality of regions, and a clock is supplied to each of the regions. In addition, a data transfer controller is provided with a clock controller and an address determination unit. Thus, among the physically divided regions, the clock and a control signal are supplied only to the region selected by the address determination unit, and the clock and the control signal are not supplied to the unselected region.
According to Japanese Patent Laying-Open No. 2002-207541, it is an object to accurately reduce power consumption of a system without considering an interrupt level. A bus controller includes access decision means for deciding a period during which no access occurs to a device, and control signal generation means capable of generating a signal for shifting the device to a low-power-consumption mode in the period during which no access occurs to the device, based on the decided result of the access decision means. The power consumption of the system can be properly reduced by shifting the device to the low-power-consumption mode in the period during which no access occurs to the device to reduce the power consumption in the device.
According to Japanese Patent Laying-Open No. 11-250658, it is an object to realize low power consumption of a semiconductor device by active/inactive control of an internal timing clock signal. A clock synchronous semiconductor device for interpreting chip-selected and supplied commands includes means for generating a first timing clock signal for operating a command interpreting circuit and means for generating a second timing clock signal for operating inner circuits according to the command interpret result. In a chip-unselected state, no circuit operation of the command interpret system is needed, so that the generating means performs the clock signal generating operation in the chip-selected state and stops the clock signal generating operation in the chip-unselected state to contribute to the low power consumption. The semiconductor device performs the internal operation according to commands even in the chip-unselected state and the generating means continues the clock signal generating operation even in the chip-unselected state to ensure a normal operation of the semiconductor device.
However, according to the inventions disclosed in Japanese Patent Laying-Open No. 2003-248652, and Japanese Patent Laying-Open No. 2002-207541, a memory having a low-power-consumption memory controller is not described in detail. In addition, according to the invention disclosed in Japanese Patent Laying-Open No. 11-250658, a detailed description is not given of an operation for controlling supply of a clock signal or a power supply with a changing load and a data capacity value.
Other object and new features will become more apparent from the description of this specification and accompanying drawings.